The present invention relates to a semiconductor integrated circuit device and particularly to the technique for preventing breakdown of an element by clamping unwanted high voltage when it is applied to an input terminal of the same semiconductor integrated circuit device.
It is important in a semiconductor integrated circuit to assure static electricity dielectric strength. As the technique for attaining the static electricity dielectric strength of the semiconductor integrated circuit, the technique for effective application of the integration area and releasing sudden voltage change such as surge voltage with the simplified structure is well known as described, for example, in the Japanese Unexamined Patent Publication No. Hei 11 (1999)-243639. According to this technique, a change signal which changes corresponding to generation of change in the voltage of the supplied DC voltage is generated and the switching control is conducted for the switching element pair to eliminate change of voltage based on the switching element pair for complementarily outputting the signal to the external circuit and the given input signal and the signal generated by the signal generating unit.
Moreover, the Japanese Unexamined Patent Publication No. Hei 10 (1998)-303314 discloses the technique to prevent input of static electricity to an input circuit when a surge voltage is applied. According to this technique, input of static electricity to the input circuit can be prevented by providing an input circuit which is connected to the power source line and the ground line and is also given the signal from the input terminal to process this signal and an input protection circuit in the power source side for bypassing, to the power source line, charges due to the first surge voltage inputted to the input terminal in the power source voltage direction or a power source protection circuit connected between the power source line and the ground line for bypassing, to the ground line, charges due to the first surge voltage bypassed to the power source line with the input protection circuit in the power source side.
Moreover, a circuit technique is also known in which the clamp circuit is stacked in two stages in the semiconductor integrated circuit to which the power source of the higher level exceeding the dielectric strength of a MOS transistor is supplied (for example, U.S. Pat. No. 5,907,464). In such a circuit, to the intermediate node which is formed by stacking in two stages the clamp circuit, an intermediate potential generated by an intermediate potential generating circuit is supplied. The intermediate potential generating circuit is formed of the serial connection of two p-channel type MOS transistors and the power source is divided with the serial connection circuit of these MOS transistors.
In the technique where the clamp circuits are stacked in two stages, an intermediate potential is generated with a serial connection circuit of two elements (for example, p-channel MOS transistor) and this potential is supplied to an intermediate node in the semiconductor integrated circuit device to which a high level power source exceeding the dielectric strength of MOS transistor is supplied, impedance between the high potential side power supply and low potential side power source becomes two times the impedance of single stage of the clamp circuit. According to the investigation by the inventors of the present invention, it has been found that if impedance is not sufficiently lower, the clamp circuit cannot sufficiently show an over-current bypassing function and therefore improvement in static electricity dielectric strength may be interfered.
Therefore, an object of the present invention is to provide the technique for clamping potential of unwanted level with a low impedance in the case where the clamp circuits are stacked in two stages.
The above-described and other objects and the novel features of the present invention will become more apparent from the description of this specification and the accompanying drawings.
The typical inventions disclosed in the present invention will be briefly described as follows.
Namely, in a semiconductor integrated circuit device including an input terminal for a high potential side power source, an input terminal for a low potential side power source and an internal circuit which is operated when the power source for internal circuit of the level lower than voltage of the high potential side power source is supplied, the first clamp circuit for clamping the voltage of unwanted level and the second clamp circuit which is vertically stacked on the first clamp circuit are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit.
In the internal circuit, capacitors for reducing noise included in the power source for internal circuit are provided in various points through coupling with the power source for internal circuit and the low potential side power source. Therefore, the composite capacitance of these capacitors becomes large and the impedance can controlled to the lower value.
According to the means described above, since the power source for internal circuit which is provided as the operation power source of the internal circuit is supplied to the intermediate node, a capacitor which is originally provided in the internal circuit is allocated in parallel with the first clamp circuit. Accordingly, an impedance is reduced and thereby potential difference due to an over-current flowing into a chip becomes small. As a result, a larger over-current is allowed to flow and dielectric strength for static electricity can also be improved.
In this case, the internal circuit described above may be configured with inclusion of a logic circuit which is formed of a thin film transistor coupled with the power source for internal circuit and a noise reduction capacitor provided between the power source for internal circuit and low potential side power source.
Moreover, it is also possible to provide a power source generating circuit for internal circuit in order to generate the power source for internal circuit by lowering the voltage of the high potential side power source.
In addition, an output circuit which can output a signal to the external circuit when the power source for input/output circuit different from the power source for internal circuit is supplied and the third clamp circuit provided between the power source for input/output circuit and the low potential side power source to clamp the voltage of unwanted level may also be provided.
An input terminal and an input circuit which is operated when the power source for internal circuit is supplied to fetch the signal transferred via the input terminal may also be provided and thereby the input circuit may be formed of an input transistor for obtaining the signal fetched via the input terminal and a diode for preventing static electricity breakdown to form the continuity route to the power source for the input/output circuit.
When the first clamp circuit is coupled with the low potential side power source and the second clamp circuit is coupled with the high potential side power source, the second clamp circuit may be comprised of a time constant circuit forming a reference voltage within the range of the predetermined time constant, an inverter circuit which can detect a potential difference between the high potential side power source and the power source for internal circuit based on the reference voltage, a MOS transistor which can terminating the high potential side power source and power source for internal circuit based on the output logic of the inverter circuit, and a resistor for impeding a through-current flowing into the MOS transistor and inverter circuit during the normal operation.
Moreover, it is also possible to include a rewiring layer having a lower wiring resistance to the wiring in the high potential side power source, low potential side power source and power source for internal circuit.